Implementation of Interface between AXI Protocol and DDR3 Memory for SOCFor High Speed Fir Filter Using Distributed Arithmetic

This project deals with implementation of interface for efficient SOC. It accepts the Read / write commands from AXI and convert into DDR3 access.AXI protocol is an open standard on chip interconnect specification for the connection & management of functional blocks in SOC. In this project, an interface between a master (processor/user) & slave (DDR3 memory) was designed. This interface will transfer the data from master to slave & vice versa. This interface implemented is called as DDR3 Controller, Which is specially targated for the DDR3 memory Apart from the designing DDR3 controller, The communication is achieved between the master & the slave using various resd / write commands of AXI protocol .Certain novel features of AXI protocol like variable length burst (from 1 to 16 data transfer per burst) & fixed wrapping burst are included in the design to achieve the data transfer.Our design has been implemented with respect to latency reduction and improvement in various performance parameters and the design is simulated Modelsim Synthesized on Xilinix successfully. Keywords— DDR3 memory, AXI interfaces, AXI access manager, DDR3 memories, AXI protocol operation. ——————————  ——————————